Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

48 minutes ago
Full-time
Senior
Quality Assurance and Testing
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002

Description

  • Own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using industry-standard tools.
  • Develop, maintain, and optimize physical verification flows for advanced-node SoCs.
  • Interpret foundry Design Rule Manuals and translate rule updates into verified flow changes.
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
  • Perform ESD verification to validate protection strategies, current paths, and CDM/HBM compliance.
  • Drive tapeout readiness by coordinating signoff across block-level, top-level, and Hard IP design teams.
  • Work directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Develop and modify design flows to meet chip integration and design quality requirements.
  • Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of ASIC and/or physical design flow development experience in industry.
  • Deep understanding of SoC top-level physical design flows, including floorplanning, I/O, bump and RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, and interface planning.
  • Experience integrating IP such as memories, I/Os, analog IPs, SerDes, and DDR.
  • Deep expertise in DRC, LVS, PERC, and ESD verification methodologies.
  • Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus.
  • Direct foundry DRM experience reading, interpreting, and implementing complex rule decks.
  • Experience at advanced nodes, preferably 4nm and below.
  • Experience with large SoC designs greater than 10M gates and frequencies above 1GHz.
  • Strong scripting skills in csh/bash, Perl, Python, TCL, Makefile, or similar.
  • Ability to work extended hours and weekends as needed to meet critical project milestones.
  • Must meet ITAR export eligibility requirements as a U.S. citizen or national, lawful permanent resident, refugee, asylee, or otherwise eligible for authorization.

Interested in this position?

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