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Design Verification Engineer (Silicon Engineering)

1 hour, 28 minutes ago
United States
Full-time
Junior
Test Engineer
Quality Assurance and Testing
MATLAB Python Verilog
Apply Now
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 191

Description

  • Own digital ASIC verification at both block and system level.
  • Write and review test plans, and develop test harnesses and test sequences.
  • Build SystemVerilog testbench infrastructure for design verification, including UVM and non-UVM environments.
  • Verify DSP blocks and other complex digital designs.
  • Run regressions and drive code and functional coverage to closure.
  • Automate test case generation using Python and MATLAB.
  • Support pre-silicon verification, chip bring-up, and post-silicon validation.
  • Work hands-on across cross-disciplinary teams to fully verify complex digital designs.

Requirements

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and testbench development.
  • Experience with verification methodologies such as UVM (preferred).
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Strong object-oriented programming knowledge.
  • Strong problem-solving and coding skills.
  • Experience in constrained random verification.
  • Experience developing test plans, coverage models, and analyzing verification results.
  • Experience with scripting languages, such as Python, for automation.
  • RTL design, chip bring-up, and post-silicon validation experience (preferred).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must meet ITAR requirements and be a U.S. citizen/national, lawful permanent resident, refugee, asylee, or otherwise eligible for required U.S. State Department authorizations.

Benefits

  • Pay range of $125,000–$145,000 per year for Design Verification Engineer Level I.
  • Pay range of $140,000–$175,000 per year for Design Verification Engineer Level II.
  • Eligibility for long-term incentives, including company stock, stock options, or long-term cash awards.
  • Potential discretionary bonuses.
  • Employee Stock Purchase Plan with the ability to buy additional stock at a discount.
  • Comprehensive medical, vision, and dental coverage.
  • 401(k) retirement plan, short- and long-term disability insurance, and life insurance.
  • Paid parental leave, 3 weeks of paid vacation, 10 or more paid holidays per year, and 5 days of sick leave per year for exempt employees.

Interested in this position?

Apply directly on the company website

Apply Now

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