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Senior ASIC Emulation Engineer

3 weeks, 6 days ago
United States
Full-time
Senior
Embedded Systems Engineer
Quality Assurance and Testing
C C++ CI/CD Perl Python Verilog
Apply Now

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised
View All Jobs 7

Description

  • Build, integrate, and maintain full-chip, multi-chip, and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
  • Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
  • Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
  • Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces for diverse system use cases.
  • Support system-level testing by enabling full hardware/software integration and end-to-end workload validation.
  • Help the DV team run targeted tests in emulation and optimize flows to reduce simulation bottlenecks.
  • Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and debug support.
  • Run emulation workloads, triage failures, perform root-cause analysis, and collaborate to resolve issues.
  • Maintain and enhance automation for compile flows, regression management, and continuous integration.
  • Participate in architecture reviews and microarchitecture discussions, and support design-for-emulation best practices.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in ASIC/SoC development focused on emulation.
  • Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
  • Hands-on expertise with major emulation platforms such as Palladium, ZeBu, or Veloce, including model build, debug, and performance optimization.
  • Proficiency with scripting languages such as Python, Perl, or TCL for automation and tooling.
  • Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.
  • Familiarity with buses and protocols such as APB, AHB, AXI, JTAG, and SPI.
  • Experience driving cross-functional debug across RTL, DV, firmware, physical design, and validation teams.
  • Understanding of pre- and post-silicon debug methodologies and correlation workflows.
  • Experience with FPGA prototyping platforms, low-power modes, analog/mixed-signal behavioral models, or SERDES/high-speed protocols such as PCIe, Ethernet, and USB is preferred.

Benefits

  • Base salary of $170,000–$250,000 plus equity.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off.
  • Life insurance.
  • Paid parental leave.
  • Additional perks and benefits package.
  • Reasonable accommodation support during the application and interview process.

Interested in this position?

Apply directly on the company website

Apply Now

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