Astera Labs

Astera Labs | Intelligent Connectivity Platform for Cloud and AI Infrastructure Purpose built connectivity solutions to remove performance bottlenecks in compute intensive workloads, such as AI and machine learning Astera Labs Inc., headquartered in th...

Industrial Conglomerates

Industrials

51-250 (210)

Founded 2017

$206M raised

14 open positions

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Principal Digital Design Engineer

1 day ago

India

Lead

Embedded Systems Engineer

IoT and Embedded Systems

Git Perl Python Shell Scripting Verilog

Apply Now

Astera Labs

Industrial Conglomerates

51-250

Founded 2017

$206M raised

View All Jobs 14

Description

Drive the microarchitecture and RTL implementation of complex digital IPs and SoC subsystems.
Translate architectural specifications into efficient, high-quality RTL designs.
Define scalable and reusable architectures for high-performance silicon products.
Optimize designs for performance, power, area, reliability, and testability.
Participate in architecture reviews and influence key technical decisions.
Design and implement synthesizable RTL using Verilog/SystemVerilog.
Develop high-speed datapaths, control logic, arbitration schemes, finite state machines, and protocol engines.
Ensure RTL quality through design reviews, linting, CDC/RDC analysis, and synthesis validation.
Collaborate with Verification, Physical Design, Firmware, Validation, and System Engineering teams.
Support silicon bring-up, post-silicon debugging, and customer issue resolution.
Provide technical leadership across multiple design programs and mentor engineers.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
10+ years of digital design experience for Principal Engineer level.
15+ years of digital design experience with demonstrated technical leadership for Senior Principal Engineer level.
Strong expertise in Verilog/SystemVerilog RTL development.
Proven experience delivering multiple successful silicon tape-outs.
Strong understanding of digital logic design, computer architecture, and SoC integration.
Experience with synthesis, lint, CDC/RDC, STA, and design sign-off flows.
Excellent debugging and analytical skills.
Experience with CXL, PCI Express, Ethernet MAC/PCS/PMA, or other high-speed connectivity IP preferred.
Experience with AI accelerator or data center SoCs, packet processing, DMA engines, memory controllers, DFT, or low-power design techniques preferred.
Experience with Synopsys Design Compiler, Cadence Genus, SpyGlass, Git, and scripting languages such as Python, Tcl, Perl, or Shell preferred.
Familiarity with chiplet architectures, heterogeneous compute systems, and high-speed interconnect technologies preferred.

Interested in this position?

Apply directly on the company website

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