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Sr. ASIC DFT Engineer (Silicon)

3 hours, 16 minutes ago
United States
Full-time
Senior
Hardware Engineer
Quality Assurance and Testing
C++ Embedded Systems Perl Python
Apply Now
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 251

Description

  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools.
  • Integrate and verify Design for Test IPs and fabrics within subsystems.
  • Set up and run ATPG tools and methodologies for stuck-at, transition, and path delay fault models, with emphasis on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF-annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and support ATE debug during silicon characterization.
  • Develop test scripts, automate workflows, and analyze data using Perl, Python, Tcl, or C++.
  • Collaborate with cross-disciplinary teams across systems, firmware, architecture, design, validation, product engineering, and ASIC implementation.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design for Test engineering, post-silicon validation, and/or production testing.
  • Master’s or PhD in electrical engineering, computer engineering, physics, or a related engineering field preferred.
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
  • Hands-on experience with Automated Test Equipment platforms such as Teradyne or Advantest.
  • Experience collaborating with cross-functional teams to ensure DFT features meet production requirements, preferably using Siemens Tessent workflows.
  • Knowledge of industry standards such as IEEE 1500 and IEEE 1687, and experience with low-power DFT techniques using Siemens Tessent.
  • Experience with In-System Test, boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics.
  • Hands-on experience with Tessent Streaming Scan Network and cell-aware fault models in ATPG.
  • Excellent problem-solving and communication skills, with the ability to document strategies, report results, and present to stakeholders.
  • Ability to work in a fast-paced environment, manage multiple projects, and adapt to evolving technology nodes such as 7nm and below.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must meet ITAR eligibility requirements as a U.S. citizen or national, lawful permanent resident, refugee, asylee, or otherwise eligible for required U.S. Department of State authorization.

Benefits

  • Base salary range of $135,000 to $160,000 for Level 1 and $155,000 to $185,000 for Level 2.
  • Potential long-term incentives in the form of company stock or long-term cash awards.
  • Potential discretionary bonuses.
  • Employee Stock Purchase Plan with the ability to buy additional stock at a discount.
  • Comprehensive medical, vision, and dental coverage.
  • 401(k) retirement plan.
  • Short- and long-term disability insurance, life insurance, and paid parental leave.
  • Three weeks of paid vacation, 10 or more paid holidays per year, and paid sick leave in accordance with company policy.

Interested in this position?

Apply directly on the company website

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