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Senior DFT Engineer

11 hours, 14 minutes ago
United States
Full-time
Senior
Embedded Systems Engineer
Quality Assurance and Testing
Apply Now

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised
View All Jobs 122

Description

  • Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan.
  • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies.
  • Own ATPG flow development and execution, including pattern generation, coverage closure, pattern optimization, and failure debug.
  • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, analog test interfaces, and BIST solutions.
  • Collaborate with RTL, verification, and physical design teams to ensure clean DFT integration and alignment with timing and physical constraints.
  • Drive DFT verification and signoff, including coverage metrics, DFT rule compliance checks, gate-level simulation, and pattern validation.
  • Support bring-up and silicon debug by analyzing tester failures, yield issues, and pattern correlation with silicon behavior.
  • Contribute to methodology development, automation, and DFT flow improvements.

Requirements

  • B.S. or M.S. in Electrical Engineering or a related field.
  • 7+ years of experience in DFT for complex SoCs.
  • Strong hands-on experience with RTL DFT insertion, including scan, compression, and test points.
  • Experience with ATPG tools and flows.
  • Deep understanding of scan architectures, compression techniques, fault models, and coverage closure strategies.
  • Experience with low-power DFT techniques.
  • Familiarity with mixed-signal integration challenges and test methodologies.
  • Strong debugging skills across RTL, gate-level, and silicon.
  • Experience with MBIST/LBIST implementation and memory repair flows, preferred.
  • Knowledge of IEEE 1149.x (JTAG/boundary scan) standards, preferred.
  • Experience with multi-voltage domain and power-aware DFT, preferred.
  • Exposure to physical design impacts on DFT such as scan chain reordering, congestion, and timing, preferred.
  • Scripting experience for automation, preferred.
  • Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs, preferred.
  • Prior involvement in A0 silicon bring-up and yield ramp, preferred.
  • Experience working in cross-functional, geographically distributed teams, preferred.
  • Must be a U.S. person or otherwise eligible for a federally issued export control license.

Benefits

  • Base salary range of $170,000 to $250,000 plus equity in the company.
  • Comprehensive benefits package.
  • Paid time off.
  • Medical, dental, and vision coverage.
  • Life insurance.
  • Paid parental leave.
  • Additional perks and benefits.
  • Reasonable accommodation support during the application and interview process.

Interested in this position?

Apply directly on the company website

Apply Now

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