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Principal ASIC Design Verification Engineer

1 hour, 37 minutes ago
United States
Full-time
Lead
Hardware Engineer
Quality Assurance and Testing
C C++ Git Perl Python Verilog
Apply Now

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised
View All Jobs 85

Description

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, perform root-cause analysis, and work with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, and assertion coverage to achieve sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to maximize test throughput and debug speed.
  • Participate in design reviews and microarchitecture discussions, and influence design-for-verification best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation teams to ensure end-to-end coverage.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Drive improvements to DV methodologies and manage external IP providers and verification partners when needed.
  • Lead verification efforts for large and complex systems and participate in ASIC team interviews.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Strong understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with simulation tools such as VCS, Xcelium, or Questa.
  • Experience with waveform debug tools such as Verdi or SimVision.
  • Experience with scripting languages such as Python, Perl, or TCL.
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, version control such as Git, CI/CD automation, and gate-level simulation.
  • Experience developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware or bare-metal coding such as C or C++.
  • Understanding of common industry-standard interfaces such as APB, AHB, and AXI.
  • Involvement in post-silicon validation planning and execution.
  • Experience with low-power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.
  • Must be a U.S. person or otherwise eligible for a federally issued export control license due to ITAR requirements.

Benefits

  • Base salary range of $190,000–$285,000 plus equity in the company.
  • Compensation determined by knowledge, skills, education, and experience.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off.
  • Life insurance.
  • Paid parental leave.
  • Additional perks and benefits included in the overall benefits package.

Interested in this position?

Apply directly on the company website

Apply Now

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