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Principal ASIC Design Verification Engineer

2 months ago
United States
Full-time
Lead
Embedded Systems Engineer
Quality Assurance and Testing
C C++ Git Perl Python Verilog
Apply Now

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised
View All Jobs 7

Description

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, perform root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional, code, and assertion coverage, and drive coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to improve test throughput and debug iteration speed.
  • Participate in design reviews and microarchitecture discussions, and influence design-for-verification best practices.
  • Work closely with architecture, RTL, DFT, firmware, physical design, and silicon validation teams to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Drive improvements to DV methodologies and manage external IP providers or verification partners when needed.
  • Take lead on large and complex systems and participate in ASIC team interviews.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Strong understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with simulation tools such as VCS, Xcelium, or Questa.
  • Experience with waveform debug tools such as Verdi or SimVision, coverage tools, and scripting languages such as Python, Perl, or TCL.
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control such as Git, CI/CD automation, and gate-level simulation.
  • Experience developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding such as C or C++.
  • Understanding of industry-standard interfaces such as APB, AHB, and AXI.
  • Experience with post-silicon validation planning and execution.
  • Experience with low power verification, analog behavioral models, physical design flows, cross-functional distributed teams, or space/telecom/RF-digital mixed systems is preferred.

Benefits

  • Base salary of $190,000–$285,000 plus equity in the company.
  • Comprehensive benefits package.
  • Paid time off.
  • Medical, dental, and vision coverage.
  • Life insurance.
  • Paid parental leave.
  • Additional perks.
  • Reasonable accommodations available during the application and interview process.

Interested in this position?

Apply directly on the company website

Apply Now

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