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Construction & Engineering

Industrials

11-50 (45)

Founded 2020

141 open positions

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Physical Design

2 days, 15 hours ago

India

Full-time

Senior

Hardware Engineer

IoT and Embedded Systems

Perl Python SOC

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Weekday

Construction & Engineering

11-50

Founded 2020

View All Jobs 141

Description

Execute the full physical design flow from netlist to GDSII.
Perform floorplanning, power planning, placement, clock tree synthesis, routing, and physical verification.
Drive timing closure to meet performance, power, and area targets.
Analyze congestion and optimize placement and routing.
Fix setup and hold timing violations across all design corners and modes.
Perform physical signoff checks including DRC, LVS, IR drop, EM, and antenna verification.
Collaborate with RTL, DFT, STA, and packaging teams to support tape-out.
Debug implementation issues and support ECO activities.
Ensure successful block-level or chip-level tape-out on advanced technology nodes.

Requirements

6+ years of hands-on experience in ASIC/SoC physical design.
Strong experience with the complete RTL-to-GDSII implementation flow.
Hands-on expertise in floorplanning, power planning, placement, CTS, routing, physical verification, and ECO implementation.
Strong timing closure experience with setup and hold optimization.
Hands-on experience with Cadence Innovus.
Experience with Synopsys ICC2 is an added advantage.
Strong knowledge of static timing analysis (STA) concepts.
Experience with IR drop, EM analysis, crosstalk, noise, and signal integrity.
Hands-on experience with Calibre for DRC/LVS signoff.
Experience with advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, 12nm, 16nm, and FinFET.
Good understanding of low-power implementation techniques such as UPF/CPF.
Experience in block-level or chip-level tape-out.
Experience with Fusion Compiler implementation flow is preferred.
Hands-on experience with Synopsys PrimeTime and PrimeTime-SI is preferred.
Experience with RedHawk or Voltus for power integrity analysis is preferred.
Knowledge of Formality and logical equivalence checking is preferred.
Experience with hierarchical SoC implementation is preferred.
Scripting skills in TCL, Python, or Perl are preferred.
Exposure to multi-voltage and multi-power domain designs is preferred.
Familiarity with 2.5D/3D IC advanced packaging technologies is preferred.
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
Excellent analytical, debugging, and communication skills.
Ability to work independently and collaboratively in a fast-paced semiconductor development environment.

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