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Design Verification Engineer (Silicon Engineering)

1 month ago
United States
Full-time
Junior
QA Engineer
Quality Assurance and Testing
MATLAB Python Verilog
Apply Now
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 278

Description

  • Own digital ASIC verification at both the block and system levels.
  • Write and review test plans, develop test harnesses, and create test sequences.
  • Develop SystemVerilog testbench infrastructure using UVM and non-UVM approaches.
  • Execute test plans, run regressions, and close code and functional coverage.
  • Automate test case generation using Python and MATLAB.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Work hands-on to fully verify complex digital designs in a cross-disciplinary engineering environment.

Requirements

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and testbench development.
  • Advanced degree in electrical engineering or computer engineering is preferred.
  • Experience with verification methodologies such as UVM is preferred.
  • Strong object-oriented programming knowledge.
  • Strong problem-solving and coding skills.
  • Experience with constrained random verification.
  • Experience developing test plans, implementing coverage models, and analyzing results.
  • Experience with scripting languages such as Python for automation.
  • RTL design, chip bring-up, and post-silicon validation experience is preferred.
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Must meet ITAR requirements as a U.S. citizen, national, lawful permanent resident, refugee, asylee, or otherwise eligible for required U.S. Department of State authorization.

Benefits

  • Pay range of $135,000 to $155,000 per year for Design Verification Engineer/Level I.
  • Pay range of $150,000 to $180,000 per year for Design Verification Engineer/Level II.
  • Potential long-term incentives, including company stock, stock options, or long-term cash awards.
  • Potential discretionary bonuses and eligibility to purchase additional stock at a discount through an Employee Stock Purchase Plan.
  • Comprehensive medical, vision, and dental coverage.
  • 401(k) retirement plan, short- and long-term disability insurance, and life insurance.
  • Paid parental leave.
  • 3 weeks of paid vacation, 10 or more paid holidays per year, and 5 days of sick leave per year for exempt employees.

Interested in this position?

Apply directly on the company website

Apply Now

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