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ASIC Design Verification Engineer

2 weeks, 6 days ago
United States
Full-time
Mid Level
QA Engineer
Quality Assurance and Testing
Git Perl Python Verilog
Apply Now

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised
View All Jobs 127

Description

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, and assertion coverage to achieve coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to support high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Strong understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with simulation tools such as VCS, Xcelium, or Questa, waveform debug tools such as Verdi or SimVision, and a coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with scripting languages such as Python, Perl, or TCL, and revision control systems such as Git.
  • Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management is preferred.
  • Familiarity with developing and integrating reference models is preferred.
  • Understanding of RTL design flows and industry-standard interfaces such as APB, AHB, or AXI is preferred.
  • Experience working in cross-functional, geographically distributed teams is preferred.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.
  • Must be a U.S. person or otherwise eligible for a federally issued export control license.

Benefits

  • Base salary range of $130,000 to $200,000 plus equity.
  • Comprehensive benefits package.
  • Paid time off.
  • Medical, dental, and vision coverage.
  • Life insurance.
  • Paid parental leave.
  • Additional perks and benefits.
  • Reasonable accommodation support during the application and interview process.

Interested in this position?

Apply directly on the company website

Apply Now

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