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Design Verification Engineer (Silicon Engineering)

1 week, 6 days ago
United States
Full-time
Junior
QA Engineer
Quality Assurance and Testing
MATLAB Python Verilog
Apply Now
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 256

Description

  • Perform digital ASIC verification at both block and system level.
  • Write and review test plans, and develop test harnesses and test sequences.
  • Build SystemVerilog testbench infrastructure using UVM and non-UVM approaches, including for DSP blocks.
  • Execute test plans, run regressions, and close code and functional coverage.
  • Automate test case generation using Python and MATLAB.
  • Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
  • Work hands-on to fully verify complex digital designs.
  • Collaborate with cross-disciplinary teams across systems, firmware, architecture, design, validation, product engineering, and ASIC implementation.

Requirements

  • Bachelor’s degree in electrical engineering, computer science, or computer engineering.
  • 1+ years of experience with design verification and test bench development.
  • Advanced degree in electrical engineering or computer engineering (preferred).
  • Experience with verification methodologies such as UVM.
  • Strong object-oriented programming knowledge.
  • Strong problem-solving and coding skills.
  • Experience in constrained random verification.
  • Experience developing test plans, implementing coverage models, and analyzing results.
  • Experience with scripting languages such as Python for automation.
  • RTL design, chip bring-up, and post-silicon validation experience (preferred).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must meet ITAR requirements and be a U.S. citizen/national, lawful permanent resident, refugee, asylee, or otherwise eligible for required U.S. Department of State authorization.

Benefits

  • Pay range of $125,000–$145,000 per year for Design Verification Engineer Level I.
  • Pay range of $140,000–$175,000 per year for Design Verification Engineer Level II.
  • Eligible for long-term incentives, including company stock, stock options, or long-term cash awards.
  • Potential discretionary bonuses and an employee stock purchase plan with discounted stock purchases.
  • Comprehensive medical, vision, and dental coverage.
  • 401(k) retirement plan, short- and long-term disability insurance, and life insurance.
  • Paid parental leave, 3 weeks of paid vacation, and 10 or more paid holidays per year.
  • 5 days of sick leave per year for exempt employees, plus various other discounts and perks.

Interested in this position?

Apply directly on the company website

Apply Now

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