K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing

Aerospace and satellite manufacturing

51-200

Founded 2022

$180M raised

7 open positions

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Senior ASIC Design Verification Engineer

2 months, 1 week ago

United States

Full-time

Senior

Hardware Engineer

Quality Assurance and Testing

C C++ CI/CD Git Perl Python Verilog

Apply Now

K2 Space Corporation

Defense and Space Manufacturing

51-200

Founded 2022

$180M raised

View All Jobs 7

Description

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, and drive root-cause analysis in collaboration with RTL designers.
Implement and maintain functional coverage, code coverage, and assertion coverage to achieve sign-off coverage closure.
Manage regression testing, simulation farms, and CI pipelines to improve throughput and debug speed.
Participate in design reviews and microarchitecture discussions, and influence design-for-verification best practices.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation teams to ensure end-to-end coverage and test.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Contribute to verification methodology improvements and engage external IP providers or verification partners when needed.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
Proficiency with simulation tools such as VCS, Xcelium, or Questa, waveform debug tools such as Verdi or SimVision, coverage tools, and scripting languages such as Python, Perl, or TCL.
Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
Experience with regression management, coverage analysis, revision control using Git, and CI/CD automation.
Understanding of industry-standard interfaces such as APB, AHB, and AXI.
Familiarity with embedded processor-based designs and firmware or bare-metal coding such as C or C++.
Experience developing and integrating reference models (preferred).
Understanding of low-power verification (preferred).
Familiarity with gate-level simulation and analog behavioral models (preferred).
Involvement in post-silicon validation planning and execution (preferred).
Experience working in cross-functional, geographically distributed teams (preferred).
Experience in space, telecom, or RF/digital mixed systems (preferred).
Must be a U.S. person or otherwise eligible for a federally issued export control license due to ITAR requirements.

Benefits

Base salary range of $170,000–$250,000, plus equity in the company.
Comprehensive medical, dental, and vision coverage.
Paid time off.
Paid parental leave.
Life insurance.
Additional perks included in the overall benefits package.
Reasonable accommodation support during the application and interview process.

Interested in this position?

Apply directly on the company website

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