Principal ASIC Physical Design Engineer

7 hours, 57 minutes ago
Full-time
Lead
IoT and Embedded Systems

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised

Description

  • Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, place and route, CTS, STA, physical verification, and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to improve performance, power, and area.
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners using foundry-qualified tools.
  • Partner with package, SI/PI, and test teams on package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors.
  • Work with EDA vendors to debug and optimize tool flows and evaluate new methodologies.
  • Support chip bring-up and debug with post-silicon and test teams.
  • Support products through production and spaceflight.
  • Contribute to developing new SoC subsystems for satellite communications and related applications.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end experience with RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools.
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore or outsourced physical design teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation using UPF or CPF.
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Exposure to radiation-hardened or space-qualified ASICs is preferred.
  • Experience with chip-package co-design or advanced packaging such as 2.5D/3D is preferred.
  • Experience driving tapeouts through TSMC or working with Gate-All-Around technologies is preferred.

Benefits

  • Base salary range of $190,000 to $280,000, plus equity in the company.
  • Comprehensive benefits package.
  • Paid time off.
  • Medical, dental, and vision coverage.
  • Life insurance.
  • Paid parental leave.
  • Additional perks as part of the overall benefits package.

Interested in this position?

Apply directly on the company website

Apply Now

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