ASIC Synthesis and Timing Engineer

1 hour, 34 minutes ago
Full-time
Junior
IoT and Embedded Systems

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised

Description

  • Work on the RTL-to-synthesis flow for block-level and top-level designs.
  • Integrate floorplan information from physical design into physical synthesis.
  • Develop and maintain methodologies, scripts, and automation to improve performance, power, and area.
  • Collaborate with front-end engineers to achieve timing closure and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners using foundry-qualified tools.
  • Own Lint, CDC, and UPF checks and coordinate issue closure.
  • Develop an end-to-end formal verification methodology from RTL to post-layout netlist.
  • Manage and technically guide external physical design partners and service vendors.
  • Work with EDA vendors to debug and optimize tool flows and evaluate new methodologies.
  • Support chip bring-up, debug, production, and spaceflight efforts with post-silicon and test teams.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 2+ years of experience in ASIC design for high-performance SoC blocks.
  • Proven end-to-end experience with RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools.
  • Strong hands-on experience with synthesis and constraint development.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience working with offshore or outsourced physical design teams or vendors.
  • Ability to resolve formal verification issues.
  • Ability to analyze and fix VCLP issues related to UPF.
  • Experience with logic equivalence check debug, functional ECO development and implementation, and low-power checking for UPF.
  • Familiarity with DFT integration and STA sign-off with functional ECO implementation.
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Exposure to radiation-hardened or space-qualified ASICs is preferred.
  • Experience driving tapeouts through TSMC is preferred.
  • Experience with Gate-All-Around technologies is preferred.
  • Experience working in cross-functional, geographically distributed teams is preferred.

Benefits

  • Base salary range of $130,000 to $200,000 plus equity in the company.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off.
  • Life insurance.
  • Paid parental leave.
  • Additional company perks and benefits.
  • Reasonable accommodation support during the application and interview process.

Interested in this position?

Apply directly on the company website

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