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Sr. ASIC DFT Engineer (Silicon)

3 hours, 40 minutes ago
United States
Full-time
Senior
Embedded Systems Engineer
Quality Assurance and Testing
C++ Embedded Systems Perl Python
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SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 251

Description

  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools.
  • Integrate and verify Design for Test (DFT) IPs and fabrics within subsystems.
  • Set up and run ATPG tools and methodologies for stuck-at, transition, and path delay fault models, with emphasis on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF-annotated gate-level simulations.
  • Create and validate DFT patterns for post-silicon bringup and support ATE debug through silicon characterization cycles.
  • Develop test scripts, automate workflows, and analyze data using Perl, Python, Tcl, or C++.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience in semiconductor Design for Test (DFT) engineering, post-silicon validation, and/or production testing.
  • Master’s or PhD in electrical engineering, computer engineering, physics, or a related engineering field is preferred.
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
  • Hands-on experience with Automated Test Equipment (ATE) platforms such as Teradyne or Advantest for high-volume manufacturing test development and debug.
  • Experience collaborating with cross-functional teams such as design, verification, and manufacturing to meet production requirements using Siemens Tessent workflows.
  • Knowledge of testability standards such as IEEE 1500 and IEEE 1687, and experience with low-power DFT techniques using Siemens Tessent.
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools.
  • Hands-on experience with Tessent Streaming Scan Network and cell-aware fault models in ATPG.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must meet ITAR requirements, including U.S. citizenship/national status, permanent residency, refugee/asylee status, or eligibility for required U.S. Department of State authorizations.

Interested in this position?

Apply directly on the company website

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