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Principal DFT Engineer (Silicon Engineering)

2 weeks, 2 days ago
United States
Full-time
Lead
Hardware Engineer
IoT and Embedded Systems
C++ Perl Python Verilog
Apply Now
SpaceX

SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the aim of revolutionizing space technology and enabling human life on other planets.

Aerospace & Defense
10K-50K
Founded 2002
View All Jobs 262

Description

  • Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST.
  • Own ATPG tools and methodologies, including pattern generation for stuck-at, transition, and path delay fault models.
  • Focus on pattern compression, diagnosis, and hierarchical test flows.
  • Provide post-silicon testing and validation support.
  • Evaluate design readiness for scan insertion using RTL and physical design Scan DRC tools.
  • Integrate and verify DFT fabrics and IP within subsystems.
  • Run and debug non-timing and SDF-annotated gate-level simulations.
  • Develop test scripts, automate processes, and analyze data using Perl, Python, Tcl, or C++.
  • Collaborate with cross-disciplinary teams across systems, firmware, architecture, design, validation, product engineering, and ASIC implementation.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 10+ years of experience working with ASICs.
  • 10+ years of experience in scan insertion and DFT setup, integration, and validation.
  • Leadership experience driving SOC DFT execution from concept through tapeout and product deployment.
  • RTL experience to trace and debug RTL connectivity issues related to DFT.
  • Ability to solve complex problems including clock domain crossings and power optimization.
  • Experience with UPF (Unified Power Format), formal verification, and DRC rule checking.
  • Familiarity with advanced silicon process and technology nodes for high-speed and low-power designs.
  • Strong implementation or integration experience with Verilog/SystemVerilog design blocks.
  • Experience working with ATE testers and test teams.
  • Ability to work extended hours and weekends as needed to meet critical milestones.
  • Must meet ITAR requirements as a U.S. citizen/national, lawful permanent resident, refugee, asylee, or eligible to obtain required authorizations.

Benefits

  • Pay range of $200,000 to $285,000 per year for the Physical Design Engineer/Principal level.
  • Eligibility for long-term incentives, including company stock, stock options, or long-term cash awards.
  • Potential discretionary bonuses and access to an Employee Stock Purchase Plan with discounted stock purchases.
  • Comprehensive medical, vision, and dental coverage.
  • 401(k) retirement plan, plus short- and long-term disability insurance and life insurance.
  • Paid parental leave.
  • 3 weeks of paid vacation, 10 or more paid holidays per year, and 5 days of sick leave per year for exempt employees.
  • Various other discounts and perks.

Interested in this position?

Apply directly on the company website

Apply Now

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