ASIC Physical Design Engineer

2 hours, 9 minutes ago
Full-time
Junior
IoT and Embedded Systems

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised

Description

  • Execute the full physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place and route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with DFT teams to ensure clean timing convergence.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, STA, EM, signal integrity, and power analysis.
  • Assist with chip-level integration, timing and functional ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Work closely with architecture, RTL, verification, and packaging teams on design integration.
  • Support integration with external partners on physical design activities.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 2+ years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools such as Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent.
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.
  • Exposure to radiation-hardened or space-qualified ASICs (preferred).
  • Experience with chip-package co-design or advanced packaging, including 2.5D/3D (preferred).
  • Familiarity with physical design service vendor management or offshore collaboration (preferred).
  • Experience with sign-off through TSMC (preferred).
  • Experience with Gate-All-Around technologies (preferred).
  • Experience working in cross-functional, geographically distributed teams (preferred).
  • Must be a U.S. person or otherwise eligible for a federally issued export control license due to ITAR requirements.

Benefits

  • Base salary range of $130,000 to $200,000, plus equity in the company.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off.
  • Life insurance.
  • Paid parental leave.
  • Additional perks as part of the overall benefits package.
  • Salary determined based on knowledge, skills, education, and experience.

Interested in this position?

Apply directly on the company website

Apply Now

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