K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing

Aerospace and satellite manufacturing

51-200

Founded 2022

$180M raised

122 open positions

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ASIC Design Verification Engineer

4 hours, 39 minutes ago

United States

Full-time

Mid Level

Test Engineer

Quality Assurance and Testing

Git Perl Python Verilog

Apply Now

K2 Space Corporation

Defense and Space Manufacturing

51-200

Founded 2022

$180M raised

View All Jobs 122

Description

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions and integrate formal verification where appropriate.
Drive constrained-random and directed testing to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, and perform root-cause analysis in collaboration with RTL designers.
Implement and maintain functional, code, and assertion coverage, and drive coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to improve test throughput and debug speed.
Participate in design reviews and microarchitecture discussions.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience in ASIC/SoC verification.
Strong understanding of SystemVerilog, digital logic, and hardware verification flows.
Proficiency with simulation tools such as VCS, Xcelium, or Questa.
Experience with waveform debug tools such as Verdi or SimVision and coverage tools.
Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
Familiarity with scripting languages such as Python, Perl, or TCL and revision control systems such as Git.
Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management (preferred).
Familiarity with developing and integrating reference models (preferred).
Understanding of RTL design flows and interfaces such as APB, AHB, or AXI (preferred).
Experience working in cross-functional, geographically distributed teams (preferred).
Experience in space, telecom, or RF/digital mixed systems is a plus.

Benefits

Base salary range of $130,000–$200,000 plus equity.
Comprehensive medical, dental, and vision coverage.
Paid time off.
Life insurance.
Paid parental leave.
Additional employee perks and benefits.
Salary determined by knowledge, skills, education, and experience level.

Interested in this position?

Apply directly on the company website

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