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Principal SerDes Bring-up Validation Engineer (2026-376)

3 hours, 18 minutes ago
United States
Full-time
Lead
Embedded Systems Engineer
Quality Assurance and Testing
BERT C C++ Python
Apply Now
Astera Labs

Astera Labs

Astera Labs | Intelligent Connectivity Platform for Cloud and AI Infrastructure Purpose built connectivity solutions to remove performance bottlenecks in compute intensive workloads, such as AI and machine learning Astera Labs Inc., headquartered in th...

Industrial Conglomerates
51-250
Founded 2017
$206M raised
View All Jobs 17

Description

  • Design, develop, and execute end-to-end bring-up and characterization plans for post-silicon validation.
  • Translate design and product requirements into test objectives, pass/fail criteria, and schedules.
  • Participate in architecture and design reviews to ensure testability and specification alignment.
  • Perform block-level bring-up, functional testing, parametric testing, interoperability checks, and performance benchmarking.
  • Build and maintain scalable automation frameworks for test execution, data capture, and analysis.
  • Debug complex failures across analog, digital, firmware, protocol, and system layers.
  • Root-cause issues to circuit, package, firmware, or protocol interactions and coordinate fixes with cross-functional teams.
  • Produce debug reports, characterization summaries, validation/compliance reports, and recommendations for improvements.
  • Develop Python test scripts and control interfaces to manage DSP and hardware platforms and automate regression suites.
  • Track validation metrics, coverage, and defect trends, and present data-driven recommendations to stakeholders.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8-12 years of hands-on experience in mixed-signal, high-speed lab environments.
  • Experience with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
  • Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers.
  • Deep understanding of NRZ and PAM4 architectures and high-speed building blocks such as PLLs, CTLE, DFE, FFE, and transmitter equalization.
  • Ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
  • Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset/link sequencing.
  • Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
  • Excellent troubleshooting skills and strong written and verbal communication.
  • MS or PhD in Electrical Engineering or a related field is preferred.
  • Hands-on proficiency with signal integrity test equipment and advanced probing is preferred.
  • Working knowledge of IEEE 802.3 Ethernet standards and Ethernet PHY validation is preferred.
  • Experience with I2C, I3C, SPI, and UART is preferred.
  • Ability to translate SI/PI simulation results into testable lab plans is preferred.

Benefits

  • Salary range of $185,000 to $240,000 depending on experience, level, and business need.
  • Eligible for discretionary bonus.
  • Eligible for incentives.
  • Eligible for benefits.
  • Inclusive hiring approach that encourages applicants from diverse backgrounds to apply.

Interested in this position?

Apply directly on the company website

Apply Now

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