Senior ASIC Package Design Engineer

2 hours, 15 minutes ago
Full-time
Senior
IoT and Embedded Systems

K2 Space Corporation

K2 Space builds high-powered satellite platforms and satellite buses for missions across LEO, MEO, and GEO, emphasizing higher payload power, large payload mass, vertical integration, and in-house manufacturing.

Defense and Space Manufacturing
51-200
Founded 2022
$180M raised

Description

  • Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
  • Lead package-level trade studies across cost, performance, power integrity, signal integrity, thermal behavior, manufacturability, and reliability.
  • Establish package design standards, methodologies, and best practices.
  • Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
  • Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
  • Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
  • Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network design, and decoupling strategy.
  • Lead thermal architecture at the package level, including lid selection, TIMs, heat spreaders, and mechanical interfaces to system cooling.
  • Drive material selection, substrate technology choices, and assembly process optimization.
  • Support vendor engagement, qualification, and production ramp for complex ASIC packages.

Requirements

  • Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
  • 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
  • Proven experience delivering high-pin-count, high-performance ASIC packages into production.
  • Strong understanding of substrate technologies and materials, package-level SI/PI fundamentals, and thermal management for power-dense ASICs.
  • Fluency in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
  • Experience working directly with OSATs and substrate vendors.
  • Knowledge of packaging qualification and test methodologies.
  • Experience with MCM or heterogeneous integration, including chiplets, interposers, and advanced laminates, is preferred.
  • Background in high-speed digital or mixed-signal SoCs is preferred.
  • Familiarity with aerospace, space, or high-reliability electronics is preferred.
  • Must be a U.S. person or otherwise eligible for a federally issued export control license due to ITAR requirements.

Benefits

  • Base salary range of $180,000 to $260,000, plus equity in the company.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off.
  • Life insurance.
  • Paid parental leave.
  • Additional perks and benefits not specifically enumerated in the posting.

Interested in this position?

Apply directly on the company website

Apply Now

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