Staff Engineer: STA Methodology & Sign-off Lead

1 hour, 27 minutes ago
Lead
IoT and Embedded Systems
EnCharge AI

EnCharge AI

EnCharge AI is a pioneering company that offers transformative technology for AI computation, providing breakthrough advances in performance, cost, and sustainability. Their cutting-edge hardware and software solutions enable state-of-the-art AI models...

Technology Hardware, Storage & Peripherals
11-50
Founded 2022
$22M raised

Description

  • Define and own full-chip SOC timing sign-off criteria, including MMMC definitions, derate strategies, and operating condition mapping.
  • Architect, deploy, and maintain STA and ECO flows that identify timing issues and physical design bottlenecks early in RTL and synthesis.
  • Evaluate, qualify, and deploy EDA tool features, with a strong emphasis on Cadence Tempus, to improve QoR and efficiency.
  • Build automation utilities in Tcl, Python, and Perl to standardize SDC management and automate timing audits.
  • Accelerate the ECO loop across distributed design teams through scalable automation infrastructure.
  • Partner with Physical Design to define clock tree synthesis methodologies and floorplanning guidelines.
  • Guide DFT and RTL teams to resolve structural bottlenecks such as NoC timing and complex CDC paths.
  • Lead the sign-off architecture and timing convergence strategy to support predictable, scalable tape-out.
  • Drive cross-functional alignment across Architecture, CAD, RTL, and Physical Design teams.

Requirements

  • 8 to 11 years of hands-on experience in VLSI design.
  • Primary experience in STA methodology, flow development, and sign-off criteria.
  • Experience with advanced process nodes such as 7nm, 5nm, or below.
  • Strong preference for experience with Cadence Tempus.
  • Deep expertise in MMMC flow architecture, hierarchical ILM/ETM vs. flat timing strategies, and SDC validation.
  • Strong understanding of waveform propagation, crosstalk, and statistical margining methods such as LVF and POCV.
  • Proven ability to architect broad flow solutions and debug systemic tool or methodology bottlenecks.
  • Strong leadership and influence skills in a fast-paced, high-growth environment.
  • B.Tech or M.Tech in Electrical/Electronics Engineering or a related field.

Interested in this position?

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